RV32I based 3 cycle pipelined CPU and accelerator experiments on PYNQ-Z2, written in Verilog. Focused on simple processor design, memory-mapped interfaces, and hardware/software integration.

FPGA-based hardware security experiments, Weak PUF readout from SRAM, AES-128 bit implementation, CPA and DFA on AES, mostly written in Verilog.

KIT FPGA Programming Praktikum (lab) WS25/26 exercises, all solved on Verilog, synthesis flow, board bring-up, and hardware debugging.