RV32I based 3 cycle pipelined CPU and accelerator experiments on PYNQ-Z2, written in Verilog. Focused on simple processor design, memory-mapped interfaces, and hardware/software integration.

FPGA-based hardware security experiments, Weak PUF readout from SRAM, AES-128 bit implementation, CPA and DFA on AES, mostly written in Verilog.

KIT FPGA Programming Praktikum (lab) WS25/26 exercises, all solved on Verilog, synthesis flow, board bring-up, and hardware debugging.

Embedded systems lab work with STM32, C/C++, UART/GPIO bring-up, device-level debugging, and practical board interaction.

Tiny low-level process monitor targeting Windows, Linux, and macOS, written in C/C++ with a focus on system-level process inspection. Not finished yet.

A simple, minimalistic text editor application built with C++17 and the Qt framework.

My personal/productivity nest, local first terminal cockpit, supports many operations, handling routine tasks, local LLM based operations. Project is ongoing.